1. Technical Field
The present disclosure relates to semiconductor devices, and, more particularly, to high performance CMOS fabrication.
2. Discussion of Related Art
In recent years the semiconductor industry has been striving to improve CMOS fabrication processing involving the removal of hardmasks without attacking source/drain regions, especially for those CMOS devices having high-k dielectrics and metal gates.
When CMOS devices are fabricated, for example, when using thick silicon on insulator (SOI) technology for better stress incorporation by epitaxial silicon germanium (e-SiGe) and epitaxial silicon carbon (e-SiC), the thick SOI requires high energy implants for butted junctions. Typically, the physical gate region's height has to be tall to prevent implant punch-through. However, to keep parasitic capacitances and module topography low the physical gate region may include both polysilicon (PC) and dielectric. For example, when gates are formed a thin PC gate may be layered on a metal gate, which, in turn, may be layered on a high-K dielectric covering the channel area. As such, the metal gate layer and high-K dielectric layer are typically covered by a hardmask to block the metal gate layer and high-K dielectric layer from deep source/drain implant.
FIG. 1 depicts such a hardmasking. SOI 110 may include implanted source/drain regions 112. Gate region 114 above channel region 116 of SOI 110 may include high-K dielectric layer 118 upon which is layered metal gate 120. PC gate 122 may be layered on metal gate 120. Hardmask 124 may cover PC gate 122. Spacers 126 may cover the sides of the gate region 114.
However, when the hardmask 124 blocks deep source/drain implants from penetrating the gate region 114, it also may block a silicidation processing of the gate region 114. In addition, low energy PC gate doping can be included to lower PC gate sheet resistance (rho) and the hardmask 124 would impede such doping.
As such, improving hardmask removal methodology such that the CMOS source/drain regions are not subject to attack, whether motivated by SOI, or where there may be a need to prevent punch-through of the dopants into metal gates and high-K dielectric layers such as for bulk Si technologies or other fabrication processes, has become an emerging requirement.